( *** NOTICE *** These pads have been validated by the MOSIS System of USC/ISI. Any modification of these pads by the user is done solely at the user's risk. Modified pads are not to be referred to as "MOSIS Pads" unless prior agreement is obtained from USC/ISI. MOSIS really intends that you use the complete (stuffed) digital or analog pad frames without modification. The individual pads and pad frame subcells are supplied only as a courtesy to those who want to build and verify their own custom pad frames. These pads were not designed to be interchangeable within the pad frame, rather, they were optimized for power and size, and require intricate editing and verification in different arrangements.); TINYCHIP PADS SET SCN (N-WELL) 2.0 MICRON 1. INTRODUCTION This 2 micron SCN (N-well) TinyChip pads set was designed with the MOSIS scalable CMOS design rules (Rev 6) at a lambda of 1.0 micron. To use these pads, get the newest Magic technology file (dated on or after than 1/19/93). All pads are laid out on a lambda grid and are designed for use with the 40PC22X22 Standard Frame. 2. CONTENTS OF THE DIGITAL PADS SET * List blank.CIF balnk with only bonding metals gnd.CIF internal GND power supply - not connected to pad GND vdd.CIF internal Vdd power supply - not connected to pad Vdd in.CIF input pad - a derivative from I/O pad io.CIF input/output pad out.CIF output pad - a derivative from I/O pad cg.CIF GND Bottom Left corner pad CG_r.CIF GND Bottom Right corner pad cv.CIF Vdd Top Left corner pad cv_r.CIF Vdd Top Right corner pad 40pc22x22_stuffed.CIF contains a complete io pad ring layout in size 2220x2250 um * Description The single most important pad in this pad set is the IO pad. From this tri-state I/O pad we derived the IN pad and the OUT pad. A circuit diagram for this tri-state I/O pad is given below. Connecting ENABLE to GND will turn this I/O pad into an input pad. Connecting ENABLE to Vdd will result an output pad. ESD protection is done with (1) Thick-Field Oxide transistor of size W/L= 600/3 microns, (2) 150 ohms N_diffusion resistor/diode, and (3) Tri-state output drivers as pair of diode clamps. * Circuit Diagram +-----+ +----| PAD | | +-----+ +-+ | Vdd | \ +---------+ +-+ / 150 ohm | | |GND \ |+--+ +--+| ENABLE | +--0|| ||0--------- Vdd | | |+--+ +--+| | | | | | |+--+ | | +---------+-------------------0|| P | | | | |+--+ | ENABLE | |+--+ +--+| ENABLEbar | | ---------|---|| ||0--+------ +------+ | |+--+ +--+| | | | IN_unbuffered | | | | |+--+ | | +---------+-------|------------|| N +---+ | | | | |+--+ | | OUT | |+--+ +--+| | | \ / ------+---|| ||---+ GND 0 |+--+ +--+| | INbar | | +---+ +---------+ | | GND \ / 0 | IN * Size These pads should fit into the standard frame 40PC22x22 with mirroring. They can also be used for other MOSIS standard frames. io, in, out, Vblank, vdd, and gnd has none-well maximum bonding box (MBB) of 200x210 microns each. The well MBB is 210x218 microns. The stuffed frame has a non-well MBB of 2220x2250 microns. There are 9 pads on each edge plus 4 corners used as Vdd and GND pads. The top edge has a GND pad in the middle and its 2 corners are Vdd pads, while the bottom edge has a Vdd pad in the middle and its 2 corners are GND pads. This gives 3 Vdd and 3 GND pads total. 3. CONTENTS OF THE ANALOG PADS SET * List gndN.CIF internal GND power supply - not connected to pad GND vddN.CIF internal Vdd power supply - not connected to pad Vdd analogN.CIF analog input/output pad llN.CIF GND Bottom Left corner pad urN.CIF Vdd Top Right corner pad 40pc22x22_stuffed_analog.CIF contains a complete io pad ring layout in size 2220x2250 um * Description ESD protection is achieved by two lateral PNP parasitic transistor in N-well (1) reverse biased diode connected to Vdd when a positive ESD stress is applied. (2) PNP transistor from GND to input when a negative ESD stress is applied. 4. SIMULATION and MEASUREMENT Both pad set have been fabricated by MOSIS for verification, but only pads in digital set are simulated and measured. Their result are listed as follows: * Delay OUTPUT Driver Load (SIMULATED) 10pF 30pF 50pF ------------+------------------------ rise time | 8ns 21ns 30ns fall time | 7ns 17ns 25ns ------------+------------------------ OUTPUT Driver Load (MEASURED) no load 10pF 22pF 47pF ------------+-------------------------------- prop. delay | 8.6ns 10.8ns 13.0ns 18.5ns (0 to 1) | ------------+-------------------------------- INPUT Driver Load (SIMULATED) load: load: load: INbar/IN INbar/IN INbar/IN 0.5/1pF 1/2pF 2/4pF prop/rise/fall prop/rise/fall prop/rise/fall signal signal delay/time/time delay/time/time delay/time/time ------ ------ --------------- --------------- --------------- PAD INbar 1.1/3.9/2.0 1.6/5.5/3.0 2.2/8.5/4.5 INbar IN 2.2/3.0/2.2 2.2/5.0/3.5 3.8/8.5/6.5 * DC Current Capability Maximum current :: 11 mA per I/O pad with 50pF loading 5. Magic CIF input In Magic, Berkeley's layout editor, use ":cif is lambda=1.0(nwell)" to specify the appropriate CIF input style before using ":cif read ..." command.